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MAX1005EEE Datasheet(PDF) 2 Page - Maxim Integrated Products |
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MAX1005EEE Datasheet(HTML) 2 Page - Maxim Integrated Products |
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2 / 8 page ![]() IF Undersampler 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ∞, TA = TMIN to TMAX, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VCCA to AGND ........................................................-0.3V, +6.0V VCCD to DGND ........................................................-0.3V, +6.0V VCCA to VCCD ...................................................................±6.3V Digital I/O Pins (D0–D6, CLK, RXEN, TXEN) to DGND .................................-0.3V to (VCCD + 0.3V) or 6.0V (whichever is smaller) Analog I/O Pins (AIO+, AIO-) to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V) AGND to DGND........................................................-0.3V, +0.3V Power Dissipation (TA = +70°C) QSOP (derate 5.90mW/°C above 70°C) ......................470mW Operating Temperature Ranges MAX1005CEE .....................................................0°C to +70°C MAX1005EEE...................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, <10sec)...........................+300°C (Notes 9, 10) AIO+ = AIO- (Note 4) (Notes 6, 7) (Note 3) (Note 5) CONDITIONS -42 dB -42 -24 THD Total Harmonic Distortion mV 368 400 432 VIN Full-Scale Input Range LSB ±2 Offset Error LSB ±0.2 DNL Differential Nonlinearity LSB ±0.2 INL Integral Nonlinearity Bits 5 N Resolution dB 67 PSR Power-Supply Rejection CLK period 0.5 DAC Latency dBc -50 Clock Feedthrough µs 0.7 2.4 tWAKE Wakeup Time Exiting Shutdown LSB ±0.2 ±1 INL Integral Nonlinearity Bits 7 N Resolution -28 dBc THD+N Total Harmonic Distortion plus Noise 39 dBc 28 39 SFDR Spurious-Free Dynamic Range LSB ±0.2 ±1 DNL Differential Nonlinearity LSB ±1 Offset Error mVp-p 736 800 864 VOUT Transmit Full-Scale Output Voltage UNITS MIN TYP MAX SYMBOL PARAMETER VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 3.0V VCC_ (A or D or both) = 3.0V ±100mVp-p at 100kHz VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V (Note 9) (Note 9) 4.9 Bits 4.5 4.9 ENOB Effective Number of Bits 44 dB 24 44 SFDR Spurious-Free Dynamic Range VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V TRANSMIT DAC DC ACCURACY (Note 1) TRANSMIT DAC DYNAMIC PERFORMANCE (TA = +25°C) (Note 2) TRANSMIT ADC DC ACCURACY (Note 8) RECEIVE ADC DYNAMIC PERFORMANCE (TA = +25°C) (Note 8) |
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