+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

______________________________________________________________________________________

13

conversion already in progress. When internal clock

mode is selected, SSTRB does not go into a high-

impedance state when CS goes high.

Figure 9 shows the SSTRB timing in internal clock

mode. In this mode, data can be shifted in and out of

the MAX1246/MAX1247 at clock rates exceeding

above 1.5µs.

Data Framing

The falling edge of CS does not start a conversion.

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte. A

conversion starts on SCLK’s falling edge, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as follows:

The first high bit clocked into DIN with CS low any

OR

The first high bit clocked into DIN after bit 5 of a con-

version in progress is clocked onto the DOUT pin.

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

SSTRB

CS

SCLK

DIN

DOUT

1

4

8

12

18

20

24

START

SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

B11

MSB

B10

B9

B2

B1

B0

LSB

FILLED WITH

ZEROS

IDLE

CONVERSION

7.5

µs MAX

(SHDN = FLOAT)

2

3

5

6

7

9

10

11

19

21

22

23

ACQUISITION

IDLE

A/D STATE

1.5

µs

Figure 8. Internal Clock Mode Timing

• • •

• • •

• • •

• • •

PD0 CLOCKED IN

SSTRB

SCLK

CS

• • •

• • • •

•

Figure 7. External Clock Mode SSTRB Detailed Timing