Fault-Protected, 12-Bit ADCs

with Software-Selectable Input Range

16

______________________________________________________________________________________

X = Don’t care.

CONTROL BIT

SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)

SMP

BIT7

0

SPI Data Input Sample Phase. Input data is sampled at the middle of the data output

time.

CKE

BIT6

1

SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock.

D/A

BIT5

X

Data Address Bit

P

BIT4

X

Stop Bit

S

BIT3

X

Start Bit

R/W

BIT2

X

Read/Write Bit Information

UA

BIT1

X

Update Address

BF

BIT0

X

Buffer Full Status Bit

Table 6. Detailed SSPSTAT Register Contents—PIC16/PIC17

X = Don’t care.

CONTROL BIT

SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)

WCOL

BIT7

X

Write Collision Detection Bit

SSPOV

BIT6

X

Receive Overflow Detection Bit

SSPEN

BIT5

1

Synchronous Serial-Port Enable Bit:

0: Disables serial port and configures these pins as I/O port pins.

1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.

CKP

BIT4

0

Clock Polarity Select Bit. CKP = 0 for SPI master mode section.

SSPM3

BIT3

0

SSPM2

BIT2

0

SSPM1

BIT1

0

SSPM0

BIT0

1

Table 5. Detailed SSPCON Register Contents—PIC16/PIC17

1

…111

1

…110

1

…101

1

…100

0

…011

0

…010

0

…001

0

…000

01

2

OUTPUT CODE

INPUT VOLTAGE (LSB)

1 LSB =

FS

4096

3

4092

4094

FS

Figure 13a. Unipolar Transfer Function

0

…111

0

…110

0

…101

0

…100

0

…001

0

…000

1

…111

1

…011

1

…010

1

…001

1

…000

-2048

-2046

OUTPUT CODE

(TWO’S COMPLEMENT)

INPUT VOLTAGE (LSB)

1 LSB =

2

FS

4096

-1 0 +1

+2045 +2047

Figure 13b. Bipolar Transfer Function