Tracking, Sinking and Sourcing, Synchronous Buck

Controller for DDR Memory and Termination Supplies

16

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The actual microfarad capacitance value required

relates to the physical size needed to achieve low ESR,

as well as to the chemistry of the capacitor technology.

As a result, the capacitor is usually selected by ESR

and voltage rating rather than by capacitance value

(this is true of tantalums, OS-CONs, POSCAPs, and

other electrolytics).

Input Capacitor Selection

The input capacitor must meet the ripple current

Nontantalum chemistries (ceramic, aluminum, or OS-

CON) are preferred due to their superior surge current

capacity:

Setting the Current Limit

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

half of the ripple current. For example:

MAX1917, the minimum current-limit threshold (100mV

default setting) is 50mV. Use the worst-case maximum

ture. A good general rule is to allow 0.5% additional

resistance for each °C of temperature rise.

When adjusting the current limit, use a 1% tolerance

in the current-limit tolerance.

Setting the Voltage Positioning

inductor before the output capacitor, sets the droop

age at the maximum load current, including ripple, is

just above the lower limit of the output tolerance:

given by:

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty-factor

extremes. For the high-side MOSFET, the worst-case

power dissipation due to resistance occurs at minimum

input voltage:

Generally, a small high-side MOSFET is desired in order

to reduce switching losses at high input voltages.

power-dissipation limits often limits how small the

MOSFET can be. Again, the optimum occurs when the

losses. Calculating the power dissipation in Q1 due to

switching losses is challenging because it must allow for

difficult-to-quantify factors that influence the turn-on and

turn-off times. These factors include the internal gate

resistance, gate charge, threshold voltage, source

inductance, and PC board layout characteristics. The fol-

lowing switching loss calculation provides only a very

rough estimate and is no substitute for breadboard eval-

uation, preferably including a check using a thermocou-

ple mounted on Q1:

For the low-side MOSFET, Q2, the worst-case power

dissipation always occurs at maximum input voltage:

PD SWITCHING

CV

f

I

I

RSS

IN MAX

LOAD

GATE

()

()

=

×× ×

2

R

VV

V

I

DRP

OUT TYP

OUT MIN

RIPPLE

OUT MAX

<

−−

()

(

)

()

/ 2

II

VV

V

V

RMS

LOAD

OUT

IN

OUT

IN

=×

×−

()















