PEX8718 datasheet(2/4 Pages) AVAGO

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PEX8718, PCI Express Gen3 Switch, 16 Lanes, 5 Ports

Page 2 of 4

10Sep12; v1.0

The PEX8718 also provides several ways to configure

its registers. The device can be configured through

strapping pins, I

2C interface, host software, or an

optional serial EEPROM. This allows for easy debug

during the development phase, performance monitoring

during the operation phase, and driver or software

upgrade.

Dual-Host & Failover Support

In Single-Host

mode, the PEX8718

supports a Non-

Transparent (NT)

Port, which enables

the implementation

of dual-host

systems for

redundancy and host

failover capability.

The NT port allows

systems to isolate host memory domains by presenting

the processor subsystem as an endpoint rather than

another memory system. Base address registers are used

to translate addresses; doorbell registers are used to send

interrupts between the address domains; and scratchpad

registers (accessible by both CPUs) allow inter-

processor communication (see Figure 3).

Hot-Plug for High Availability

Hot plug capability allows users to replace hardware

modules and perform maintenance without powering

down the system. The PEX8718 Hot-Plug capability

feature makes it suitable for High Availability (HA)

applications. One downstream ports include a Standard

Hot Plug Controller. If the PEX8718 is used in an

application where one or more of its downstream ports

connect to PCI Express slots, each port’s Hot-Plug

Controller can be used to manage the Hot-Plug event of

its associated slot. Every port on the PEX8718 is

equipped with a Hot-Plug control/status register to

support Hot-Plug capability through external logic via

the I

2C interface.

SerDes Power and Signal Management

The PEX8718 supports software control of the SerDes

outputs to allow optimization of power and signal

strength in a system. The PLX SerDes implementation

supports four levels of power – off, low, typical, and

high. The SerDes block also supports loop-back modes

and advanced reporting of error conditions, which

enables efficient management of the entire system.

Interoperability

The PEX8718 is designed to be fully compliant with the

PCI Express Base Specification r3.0, and is backwards

compatible to PCI Express Base Specification r1.1 and

r1.0a. Additionally, it supports auto-negotiation, lane

reversal, and polarity reversal. Furthermore, the

PEX8718 is tested for Microsoft Windows Logo

compliance. All PLX switches undergo thorough

interoperability testing in PLX’s Interoperability Lab

and compliance testing at the PCI-SIG plug-fest.

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