PEX8780 datasheet(2/5 Pages) AVAGO

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PEX8780, PCI Express Gen3 Switch, 80 Lanes, 20 Ports

Page 2 of 5

24July12; v1.2

The PEX8780 also

provides several ways to

configure its registers. The

device can be configured

through strapping pins,

2C interface, host

software, or an optional

serial EEPROM. This

allows for easy debug

during the development

phase, performance

monitoring during the

operation phase, and driver or software upgrade.

Dual-Host & Failover Support

In Single-Host mode, the PEX8780 supports a Non-

Transparent (NT) Port, which enables the

implementation of dual-host systems for redundancy

and host failover capability. The NT port allows systems

to isolate host memory domains by presenting the

processor subsystem as an endpoint rather than another

memory system. Base address registers are used to

translate addresses; doorbell registers are used to send

interrupts between the address domains; and scratchpad

registers (accessible by both CPUs) allow inter-

processor communication (see Figure 3).

Multi-Host & Failover Support

In Multi-Host mode, PEX8780

can be configured with up to

four upstream host ports, each

with its own dedicated

downstream ports. The device

can be configured for 1+1

redundancy or N+1 redundancy.

The PEX8780 allows the hosts

to communicate their status to

each other via special door-bell

registers. In failover mode, if a host fails, the host

designated for failover will disable the upstream port

attached to the failing host and program the downstream

ports of that host to its own domain. Figure 4a shows a

two host system in Multi-Host mode with two virtual

switches inside the device and Figure 4b shows Host 1

disabled after failure and Host 2 having taken over all of

Host 1’s end-points.

Hot-Plug for High Availability

Hot-Plug capability allows users to replace hardware

modules and perform maintenance without powering

down the system. The PEX8780 Hot-Plug capability

feature makes it suitable for High Availability (HA)

applications. One downstream port includes a Standard

Hot-Plug Controller. If the PEX8780 is used in an

application where one or more of its downstream ports

connect to PCI Express slots, each port’s Hot-Plug

Controller can be used to manage the Hot-Plug event of

its associated slot. Every port on the PEX8780 is

equipped with a Hot-Plug control/status register to

support Hot-Plug capability through external logic via

the I

2C interface.

SerDes Power and Signal Management

The PEX8780 supports software control of the SerDes

outputs to allow optimization of power and signal

strength in a system. The PLX SerDes implementation

supports four levels of power – off, low, typical, and

high. The SerDes block also supports loop-back modes

and advanced reporting of error conditions, which

enables efficient management of the entire system.

Interoperability

The PEX8780 is designed to be fully compliant with the

PCI Express Base Specification r3.0, and is backwards

compatible to PCI Express Base Specification r1.1 and

r1.0a. Additionally, it supports auto-negotiation, lane

reversal, and polarity reversal. Furthermore, the

PEX8780 is tested for Microsoft Windows Logo

compliance. All PLX switches undergo thorough

interoperability testing in PLX’s Interoperability Lab

and compliance testing at the PCI-SIG plug-fest.

performancePAK

Exclusive to PLX, performancePAK is a suite of unique

and innovative performance features which allows

PLX’s Gen 3 switches to be the highest performing Gen

3 switches in the market today. The performancePAK

features consists of Multicast, and Dynamic Buffer Pool.

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