SPI and Microwire

When using SPI or QSPI, set CPOL = 0 and CPHA = 0.

Conversion begins with a

CS falling edge. DOUT goes

low, indicating a conversion in progress. Wait until

DOUT goes high or the maximum specified 8.5µs con-

version time. Two consecutive 1-byte reads are

required to get the full 12 bits from the ADC. DOUT out-

put data transitions on SCLK’s falling edge and is

clocked into the µP on SCLK’s rising edge.

The first byte contains a leading 1 and 7 bits of conver-

sion result. The second byte contains the remaining 5

bits and 3 trailing 0s. See Figure 13 for connections

and Figure 14 for timing.

QSPI

Set CPOL = CPHA = 0. Unlike SPI, which requires two

1-byte reads to acquire the 12 bits of data from the

ADC, QSPI allows the minimum number of clock cycles

necessary to clock in the data. The MAX187/MAX189

require 13 clock cycles from the µP to clock out the

12 bits of data with no trailing 0s (Figure 15). The maxi-

mum clock frequency to ensure compatibility with QSPI

is 2.77MHz.

Opto-Isolated Interface,

Serial-to-Parallel Conversion

Many industrial applications require electrical isolation

to separate the control electronics from hazardous

electrical conditions, provide noise immunity, or pre-

vent excessive current flow where ground disparities

exist between the ADC and the rest of the system.

Isolation amplifiers typically used to accomplish these

tasks are expensive. In cases where the signal is even-

tually converted to a digital form, it is cost effective to

isolate the input using opto-couplers in a serial link.

The MAX187 is ideal in this application because it

includes both T/H amplifier and voltage reference,

operates from a single supply, and consumes very little

power (Figure 16).

+5V, Low-Power, 12-Bit Serial ADCs

16

______________________________________________________________________________________

MAX187

ANALOG

INPUT

SIGNAL

GROUND

4.7

µF5

4

2

1

6

8

7

3

10

µF

0.1

µF

GND

REF

AIN

VDD

DOUT

SCLK

CS

SHDN

+5V

3k

3k

470

Ω

8

7

6

5

1

2

3

4

200

Ω

200

Ω

+5V

8

7

6

5

1

2

3

4

1

2

3

4

8

7

6

5

+5V ON THIS SIDE OF

BARRIER MUST BE ISOLATED POWER

6N136

6N136

6N136

74HC04

74HC04

8.2k

+5V

14

11

12

10

7

6

5

4

3

2

1

15

16

D11 (MSB)

D10

D9

D8

+5V

0.1

µF

CS/START

SCLK/INPUT CLOCK

SER

SCK

RCK

SCLR

QH

QG

QF

QE

QD

QC

QB

QA

13

8

9

7

6

5

4

3

2

1

15

16

+5V

0.1

µF

13

8

14

11

12

10

74HC595

74HC595

SER

SCK

RCK

SCLR

QH

QG

QF

QE

QD

QC

QB

QA

QH

′

D0(LSB)

D1

D2

D3

D4

D5

D6

D7

Figure 16. 12-Bit Isolated ADC