Upstream CATV Amplifiers

16

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Detailed Description

Programmable-Gain Amplifier

The PGA consists of the variable-gain amplifier (VGA)

and the digital-to-analog converter (DAC), which pro-

vide better than 56dB of output level control in 0.5dB

steps. The PGA is implemented as a programmable

Gilbert-cell attenuator. The gain of the PGA is deter-

mined by a 7-bit word (D6–D0) programmed through

the serial data interface (Tables 1 and 2).

Specified performance is achieved when the input is

driven differentially. The device may be driven single

ended. To drive the device in this manner, one of the

input pins must be capacitively coupled to ground. Use

a capacitor value large enough to allow for a low-

impedance path to ground at the lowest frequency of

operation. For operation down to 5MHz, a 0.001µF

capacitor is suggested.

Output Amplifiers

The output amplifiers are Class A differential amplifiers

capable of driving +61dBmV (QPSK, MAX3514) differ-

entially. This architecture provides superior even-order

distortion performance but requires that a transformer

be used to convert to a single-ended output. In trans-

mit-disable mode, the output amplifiers are powered

down. A resistor is across the output so that the output

impedance remains matched when the amplifier is in

transmit-disable mode. Disabling the output devices

also results in low output noise.

MAX3514/MAX3516

To match the output impedance to a 75

Ω load, the

transformer must have a turns ratio (voltage ratio) of 2:1

(4:1 impedance ratio). The differential amplifier is

biased directly from the +5V supply using the center

tap of the output transformer. This provides a signifi-

cant benefit when switching between transmit mode

and transmit-disable mode. Stored energy due to bias

currents will cancel within the transformer and prevent

switching transients from reaching the load.

MAX3517

The MAX3517 uses external matching resistors to allow

matching to various load impedances through suitable

values of matching resistors and transformer turns

ratios.

Serial Interface

The serial interface has an active-low enable (CS) to

bracket the data, with data clocked in MSB first on the

rising edge of SCLK. Data is stored in the storage latch

on the rising edge of CS. The serial interface controls

Functional Diagram

MAX3514

MAX3516

MAX3517

GND

SDA SCLK

OUT-

OUT+

*MAX3514/MAX3516 ONLY

IN+

IN-

TXEN

CEXT

*

BIAS

CONTROL

SHDN

HIGH

POWER

LOW

NOISE

D/A CONVERTER

SERIAL DATA INTERFACE

CS