74LV4053_15 datasheet(5/27 Pages) PHILIPS

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74LV4053

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Product data sheet

Rev. 5 — 18 September 2014

5 of 27

NXP Semiconductors

74LV4053

Triple single-pole double-throw analog switch

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

Limiting values

[1]

To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional

switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case

there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.

[2]

The minimum input voltage rating may be exceeded if the input current rating is observed.

[3]

For DIP16 packages: above 70

C the value of P

tot derates linearly with 12 mW/K.

For SO16 packages: above 70

C the value of P

tot derates linearly with 8 mW/K.

For SSOP16 and TSSOP16 packages: above 60

C the value of P

tot derates linearly with 5.5 mW/K.

For DHVQFN16 packages: above 60

C the value of P

tot derates linearly with 4.5 mW/K.

Table 3.

Function table [1]

Inputs

Channel on

LLnY0 to nZ

nY1 to nZ

switches off

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

[1]

0.5

+7.0

IIK

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

[2] -

20

ISK

switch clamping current

VSW < 0.5 V or VSW > VCC + 0.5 V

[2] -

20

ISW

switch current

VSW > 0.5 V or VSW < VCC + 0.5 V;

source or sink current

[2] -

25

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

Tamb = 40 C to +125 C

[3]

DIP16 package

750

SO16 package

500

TSSOP16 package

500

DHVQFN16 package

500

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