622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

_______________________________________________________________________________________

9

current of the op amp at the INV pin is guaranteed to

be less than ±100nA. To set the threshold voltage

externally (i.e., via a DAC control), completely disable

the op amp by grounding the inverting terminal (INV).

externally.

The comparator is configured with an active-high LOP

output. An on-chip, 6k

Ω pull-up resistor is provided to

reduce external part count.

Setting the Loop Filter

The loop filter within the PLL consists of a transconduc-

(Figure 2). The closed-loop bandwidth of a PLL is

approximated by:

gain of the VCO, and Gm is the transconductance of

the filter amplifier. For the MAX3675, an estimated value

Because the PLL is a second-order system, a zero in

the open-loop gain is required for stability. This zero is

set by the following equation:

ance and jitter-generation performance, but also

reduces jitter-transfer performance. (Decreasing the

bandwidth has the opposite effect.)

This type of PLL is a classical second-order system.

second-order system can be approximated by:

where Mp is the magnitude of the peaking. For

specifications is not a requirement. For example, setting

width to approximately 2.2MHz (Figure 3). Loop stability

is ensured by maintaining a separation of 10x between

of the IC, and upper values are limited by the internal

high-frequency pole.

= 1 / R C

()

K

K

Gm R

DO

F

MAX3675

F(S)

GM

FIL+

FIL-

Figure 2. Loop Filter

F(s) =

Gm

s

s C

s/

1

RC

R

C

2.2 F

internal higher - order pole

z

FP

FF

F

F

ω

ω

ω

µ

ω

+









[]

=

=

=

=

1

1

52 3

z

P

.

Ω

100

1k

10k

100k

1M

10M

100M

1G

FREQUENCY (Hz)

HIGHER-

ORDER

POLE

>10x

Figure 3. Loop-Filter Response