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9DB833

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3

9DB833

REV G 082515

Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Slew rate

Trf

Scope averaging on

V/ns

1, 2, 3

Slew rate matching

∆Trf

Slew rate matching, Scope averaging on

1, 2, 4

Voltage High

VHigh

660

800

850

Voltage Low

VLow

-150

150

Max Voltage

Vmax

806

1150

Min Voltage

Vmin

-300

-1

Vswing

Scope averaging off (Differential)

300

1552

1, 2

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

375

550

1, 5

Crossing Voltage (var)

∆-Vcross

Scope averaging off

140

1, 6

2 Measured from differential waveform

6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross

absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Measurement on single ended signal using

absolute value. (Scope averaging off)

1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR

R).

For RR = 475Ω (1%), IREF = 2.32mA.

IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).

3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

-3dB point in High BW Mode (TIND)1.5

2.7

4.1

MHz

-3dB point in High BW Mode (TCOM)2

2.7

MHz

-3dB point in Low BW Mode

0.7

1.1

1.4

MHz

PLL Jitter Peaking

tJPEAK

Peak Pass band Gain

1.5

Duty Cycle

tDC

Measured differentially, PLL Mode

Duty Cycle Distortion

tDCD

Measured differentially, Bypass Mode @100MHz

-2

1,4

Bypass Mode, VT = 50% (TIND)

2500

4900

Bypass Mode, VT = 50% (TCOM)

2500

4500

1,5

tpdPLL

PLL Mode VT = 50%

-250

-50

250

Skew, Output to Output

tsk3

VT = 50%

50/60

1,5

PLL mode

1,3

Additive Jitter in Bypass Mode

1,3

1Guaranteed by design and characterization, not 100% tested in production.

2 I

REF = VDD/(3xRR).

For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.

3 Measured from differential waveform

4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

5 First number is commercial temp, second number is industrial temp.

PLL Bandwidth

Skew, Input to Output

tpdBYP

Jitter, Cycle to cycle

tjcyc-cyc

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