9DBU0741 datasheet(1/17 Pages) ICST

Part #	9DBU0741

Description	slew rate for each output

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Manufacturer	ICST [Integrated Circuit Systems]

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DATASHEET

9DBU0741 REVISION C 04/22/15

1

7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer

w/Zo=100ohms

9DBU0741

Description

The 9DBU0741 is a member of IDT's 1.5V Ultra-Low-Power

(ULP) PCIe family. It has integrated terminations for direct

connection to 100

 transmission lines. The device has 7

output enables for clock management, and 3 selectable

SMBus addresses.

Recommended Application

1.5V PCIe Gen1-2-3 Fan-out Buffer (FOB)

Output Features

• 7 – 1-167MHz Low-Power (LP) HCSL DIF pairs

w/ZO=100



Key Specifications

• DIF additive cycle-to-cycle jitter <5ps

• DIF output-to-output skew < 60ps

• DIF additive phase jitter is <300fs rms for PCIe Gen3

• DIF additive phase jitter <350s rms for SGMII

Features/Benefits

• Integrated terminations; save 28 resistors compared to

standard HCSL outputs

• 36mW typical power consumption; eliminates thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05 and 1.5V; maximum power savings

• Spread Spectrum (SS) compatible; allows SS for EMI

reduction

• OE# pins for each output; support DIF power management

• HCSL-compatible differential input; can be driven by

common clock sources

• SMBus-selectable features; optimize signal integrity to

application

• slew rate for each output

• differential output amplitude

• Device contains default configuration; SMBus interface not

required for device operation

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• 3.3V tolerant SMBus interface works with legacy controllers

• Space saving 40-pin 5x5mm VFQFPN; minimal board

space

Block Diagram

CONTROL

LOGIC

^CKPWRGD_PD#

SDATA_3.3

vOE(6:0)#

SCLK_3.3

vSADR

CLK_IN

7

CLK_IN#

DIF0

DIF1

DIF2

DIF3

DIF4

DIF5

DIF6

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