9DBV0831 datasheet(9/19 Pages) ICST

9 / 19 page

REVISION G 03/02/15

8 O/P 1.8V PCIE GEN1-2-3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB)

9DBV0831 DATASHEET

Electrical Characteristics–Low Power HCSL Outputs

Electrical Characteristics–Current Consumption

TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

dV/dt

Scope averaging on, fast setting

1.7

2.7

V/ns

1,2,3

dV/dt

Scope averaging on, slow setting

1.2

2.1

3.3

V/ns

1,2,3

Slew rate matching

ΔdV/dt

Slew rate matching, Scope averaging on

4.6

1,2,4

Voltage High

VHIGH

660

774

850

Voltage Low

VLOW

-150

150

Max Voltage

Vmax

820

1150

Min VoltageVmin

-300

-25

Vswing

Scope averaging off

300

1528

1,2

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

413

550

1,5

Crossing Voltage (var)

Δ-Vcross

Scope averaging off

140

1,6

2 Measured from differential waveform

7 At default SMBus settings.

Slew rate

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Measurement on single ended signal using

absolute value. (Scope averaging off)

1Guaranteed by design and characterization, not 100% tested in production.

3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting

Δ-Vcross to be smaller than Vcross absolute.

TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

IDDA

VDDA+VDDR, PLL Mode, @100MHz

IDD

VDD, All outputs active @100MHz

IDDO

VDDO, All outputs active @100MHz

IDDAPD

VDDA+VDDR, PLL Mode, @100MHz

0.6

IDDPD

VDD, Outputs Low/Low

IDDOPD

VDDO,Outputs Low/Low

0.01

1 Guaranteed by design and characterization, not 100% tested in production.

2 Input clock stopped.

Operating Supply Current

Powerdown Current

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