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9DMU0441 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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9DMU0441 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 11 page  DATASHEET 9DMU0441 REVISION A 09/24/14 1 ©2014 Integrated Device Technology, Inc. 2:4 1.5V PCIe Gen1-2-3 Clock Mux w/Zo=100ohms 9DMU0441 General Description The 9DMU0441 is a member of IDT's SOC-Friendly 1.5V Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has integrated output terminations providing Zo=100ohms for direct connection to 100ohm transmission lines. Each of the 4 outputs has its own dedicated OE# pin for optimal system control and power management. The part provides asynchronous and glitch-free switching modes. Recommended Application 2:4 PCIe Gen1-2-3 clock multiplexer Output Features • 4 – Low-Power (LP) HCSL DIF pairs w/Zo=100 Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF phase jitter is PCIe Gen1-2-3 compliant • Additive phase jitter @ 125MHz: 535fs rms typical (12kHz to 20MHz) • DIF output-to-output skew <50ps Features/Benefits • LP-HCSL outputs w/integrated terminations; saves 16 resistors compared to standard HCSL outputs • 1.5V operation; 26mW typical power consumption • Selectable asynchronous or glitch-free switching; allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode • Spread Spectrum Compatible; supports EMI reduction • OE# pins; support DIF power management • HCSL differential inputs; can be driven by common clock sources • 1MHz to 167MHz operating frequency • Space saving 24-pin 4x4mm VFQFPN; minimal board space Block Diagram DIF0 DIF1 DIF2 DIF3 A B 4 , ^OE(3:0)# DIF_INA DIF_INB vSW_MODE ^SEL_A_B# |
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