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MAX3831 Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX3831 Datasheet(HTML) 3 Page - Maxim Integrated Products |
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3 / 16 page ![]() +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator _______________________________________________________________________________________ 3 DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, LVDS differential load = 100 Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, LVDS differential load = 100 Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C and VCC = +3.3V.) (Note 4) TRIEN = GND IOL = 2mA IOH = 20µA VIH = 2.0V VIL = 0 CONDITIONS k Ω 6 Output Impedance V 0.4 VOL Output Voltage Low V 2.4 VOH Output Voltage High V 2.0 VIH Input Voltage High V 0.8 VIL Input Voltage Low µA -250 -50 IIH Input Current High µA -550 -100 IIL Input Current Low UNITS MIN TYP MAX SYMBOL PARAMETER Note 2: When TEST = GND, the pattern generator will consume an additional 30mA. Note 3: Guaranteed by design and characterization. (Note 7) (Note 5) 20% to 80% CONDITIONS psp-p 818 SDJ Serial-Data Output Deterministic Jitter psRMS 3.5 Mbps 622.08 Parallel Input Data Rate ns ±7.5 tes Maximum Parallel Input Skew Gbps 2.48832 Serial-Data Output Rate ps 120 tr, tf Serial-Data Output Rise/Fall Time UNITS MIN TYP MAX SYMBOL PARAMETER Figure 3 Figure 3 Mbps 622.08 PDO± Parallel-Data Output Rate Gbps 2.48832 Serial-Data Input Rate ps 100 tSU Serial-Data Setup Time ps 100 tH Serial-Data Hold Time (Note 6) psp-p 40 SRJ Serial-Data Output Random Jitter TTL INPUTS AND OUTPUTS MAX3831 PCLKO± Parallel-Clock Output Frequency MHz 622.08 MAX3831, Figure 3 tCLK-Q PCLKO to PDO_ Delay ps -100 90 300 Any differential pair tSKEW1 LVDS Differential Skew ps 65 PDO1± to PDO4± tSKEW2 LVDS Channel-to-Channel Skew ps <100 LVDS Three-State Enable Time ns 30 Note 4: AC characteristics are guaranteed by design and characterization. Note 5: Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset. Note 6: Measured with a reference clock jitter of <1psRMS. Note 7: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. MAX3832 155.52 20% to 80% LVDS Output Rise/Fall Time ps 350 4:1 MULTIPLEXER WITH CLOCK GENERATOR 1:4 DEMULTIPLEXER |
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