2.5Gbps, Low-Power, +3.3V

Clock Recovery and Data Retiming IC

_______________________________________________________________________________________

5

SDI+

SDI-

SLBI+

SLBI-

SCLKO-

SCLKO+

SDO+

SDO-

PHASE &

FREQUENCY

DETECTOR

PHADJ-

FIL+

FIL-

LOOP

FILTER

MAX3875

LOL

PHADJ+

SIS

SIS

MUX

AMP

AMP

CK

D

Q

VCO

I

Q

PECL

PECL

TTL

Figure 3. Functional Diagram

NAME

FUNCTION

PIN

27

PHADJ-

25

LOL

Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10k

Ω pull-up resistor)

23

SDO+

Positive Data Output, PECL compatible, 2.488Gbps

22

SDO-

Negative Data Output, PECL compatible, 2.488Gbps

19

SCLKO+

Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.

28

PHADJ

+

30

FIL-

Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

31

FIL+

Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

Pin Description (continued)

Detailed Description

The MAX3875 consists of a fully integrated phase-

locked loop (PLL), input amplifier, data retiming block,

and PECL output buffer (Figure 3). The PLL consists of

a phase/frequency detector (PFD), a loop filter, and a

voltage-controlled oscillator (VCO).

This device is designed to deliver the best combination

of jitter performance and power dissipation by using a

fully differential signal architecture and low-noise

design techniques.

Input Amplifier

Input amplifiers are implemented for both the main data

and system loopback inputs. These amplifiers accept a

differential input amplitude from 50mVp-p up to

800mVp-p. The bit error rate is better than 1

input signals as small as 10mVp-p, although the jitter

tolerance performance will be degraded. For interfacing

with PECL signal levels, see

Applications Information.

Phase Detector

The phase detector incorporated in the MAX3875 pro-

duces a voltage proportional to the phase difference

between the incoming data and the internal clock.

Because of its feedback nature, the PLL drives the

error voltage to zero, aligning the recovered clock to

the center of the incoming data eye for retiming. The

external phase adjust pins (PHADJ+, PHADJ-) allow the

user to vary the internal phase alignment.