6-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR

8

REVISION B 07/17/15

9FGL06 DATASHEET

Electrical Characteristics–DIF LP-HCSL Output Phase Jitter Parameters

Electrical Characteristics–Current Consumption

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

IND.

LIMIT

UNITS

Notes

PCIe Gen 1

19

23

86

ps

(p-p)

1,3,4,6

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.5

0.7

3

ps

(rms)

1,3,6

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.2

1.8

3.1

ps

(rms)

1,3,6

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.3

0.5

1

ps

(rms)

1,3,6

Phase Jitter, 12k-20M

100MHz, REF output enabled

1.5

2

N/A

ps

(rms)

2,6

Phase Jitter, PCI Express

(Common Clock

Architecture)

1

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

VDDA, All outputs active @100MHz

13

16

mA

All VDD, except VDDA and VDDIO, All outputs

active @100MHz

16

21

mA

VDDIO, All outputs active @100MHz

23

29

mA

VDDA, DIF outputs off, REF output running

0.8

1

mA

1

All VDD, except VDDA and VDDIO,

DIF outputs off, REF output running

7.59mA

1

VDDIO, DIF outputs off, REF output running

0.06

0.1

mA

1

VDDA, all outputs off

0.8

1.1

mA

All VDD, except VDDA and VDDIO, all outputs off

2.4

3

mA

VDDIO, all outputs off

0.05

0.1

mA

Powerdown Current

(Power down state and

Byte 3, bit 5 = '0')

Operating Supply Current

Wake-on-LAN Current

(Power down state and

Byte 3, bit 5 = '1')