Single/Dual/Quad, Wide-Bandwidth, Low-Power,

Single-Supply, Rail-to-Rail I/O Op Amps

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9

__________Applications Information

Rail-to-Rail Input Stage

Devices in the MAX4130–MAX4134 family of high-

speed amplifiers have rail-to-rail input and output

stages designed for low-voltage, single-supply opera-

tion. The input stage consists of separate NPN and

PNP differential stages that combine to provide an

input common-mode range that extends 0.2V beyond

the supply rails. The PNP stage is active for input volt-

ages close to the negative rail, and the NPN stage is

active for input voltages near the positive rail. The input

offset voltage is typically below 200µV. The switchover

extended to minimize the slight degradation in com-

mon-mode rejection ratio caused by the mismatch of

the input pairs. Their low offset voltage, high band-

width, and rail-to-rail common-mode range make these

op amps excellent choices for precision, low-voltage

data-acquisition systems.

Since the input stage switches between the NPN and

PNP pairs, the input bias current changes polarity as

the input voltage passes through the transition region.

Reduce the offset error caused by input bias currents

flowing through external source impedances by match-

ing the effective impedance seen by each input

(Figures 1a, 1b). High source impedances, together

with input capacitance, can create a parasitic pole that

produces an underdamped signal response. Reducing

the input impedance or placing a small (2pF to 10pF)

capacitor across the feedback resistor improves

response.

The MAX4130–MAX4134’s inputs are protected from

large differential input voltages by 1k

Ω series resistors

and back-to-back triple diodes across the inputs

(Figure 2). For differential input voltages less than 1.8V,

input resistance is typically 500k

Ω. For differential input

voltages greater than 1.8V, input resistance is approxi-

mately 2k

Ω. The input bias current is given by the fol-

lowing equation:

I

=

V

- 1.8V

2k

BIAS

DIFF

Ω

1k

1k

Figure 2. Input Protection Circuit