1GHz, Low-Power, SOT23,

Current-Feedback Amplifiers with Shutdown

12

______________________________________________________________________________________

DC and Noise Errors

(Figure 2), can be calculated with the following equation:

where:

Ω)

Ω)

Ω)

The following equation represents output noise density:

where:

√Hz)

√Hz)

The MAX4223–MAX4228 have a very low, 2nV/

√Hz

noise voltage. The current noise at the noninverting

√Hz, and the current noise at the

√Hz.

An example of DC-error calculations, using the

MAX4224 typical data and the typical operating circuit

gives:

Calculating total output noise in a similar manner yields

the following:

With a 600MHz system bandwidth, this calculates to

sigma calculation).

Communication Systems

Nonlinearities of components used in a communication

system produce distortion of the desired output signal.

Intermodulation distortion (IMD) is the distortion that

results from the mixing of two input signals of different

frequencies in a nonlinear system. In addition to the

input signal frequencies, the resulting output signal

contains new frequency components that represent the

sum and difference products of the two input frequen-

cies. If the two input signals are relatively close in fre-

quency, the third-order sum and difference products

will fall close to the frequency of the desired output and

will therefore be very difficult to filter. The third-order

intercept (IP3) is defined as the power level at which

the amplitude of the largest third-order product is equal

to the power level of the desired output signal. Higher

third-order intercept points correspond to better lineari-

ty of the amplifier. The MAX4223–MAX4228 have a typi-

cal IP3 value of 42dBm, making them excellent choices

for use in communications systems.

ADC Input Buffers

Input buffer amplifiers can be a source of significant

errors in high-speed ADC applications. The input buffer

is usually required to rapidly charge and discharge the

ADC’s input, which is often capacitive (see the section

Driving Capacitive Loads). In addition, a high-speed

ADC’s input impedance often changes very rapidly

during the conversion cycle, requiring an amplifier with

e

x

x

x

x

x

x

e

nV

Hz

n OUT

n OUT

( )

−

−

−

( )

=

+

(

)

















+

















+ 





=

.

/

1

1

3

10

50

20

10

235

2

10

10 2

12

12

2

9

2

2

e

R

R

x

i

x R

i

x R

R

e

n OUT

F

G

n

S

n

F

G

n

( )

+

−

=

+









(

(

)

[

||

1

2

2

2

V

V

x 1

R /R

I

x R

x 1

R

R

I

x R

OUT

OS

F

G

B

S

F

G

B

F

=

+

(

+









+

+

−

MAX4223

MAX4224

MAX4225

MAX4226

MAX4227

MAX4228

IN-

IN+

OUT

Figure 2. Output Offset Voltage