TPS797xx

SLVS332I – MARCH 2001 – REVISED OCTOBER 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

(2)

TPS797xx yy yz

XX is nominal output voltage (for example, 25 = 2.5V).

YYY is package designator.

Z is package quantity.

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Output voltages from 1.25V to 4.9V in 50mV increments are available through the use of probe level programming; minimum order

quantities may apply. Contact factory for details and availability.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating junction temperature range, unless otherwise noted.

–0.3V to 6V

Maximum dc output voltage

4.9V

Peak output current

Internally limited

ESD rating, HBM

2kV

ESD rating, CDM

500V

Continuous total power dissipation

See Dissipation Ratings Table

–40°C to +85°C

–65°C to +150°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

PACKAGE DISSIPATION RATINGS

DERATING FACTOR

BOARD

PACKAGE

°C/W

°C/W

POWER RATING

POWER RATING

POWER RATING

DCK

165.39

396.24

2.52mW/°C

252mW

139mW

101mW

DCK

165.39

314.74

3.18mW/°C

318mW

175mW

127mW

(1)

The JEDEC low K (1s) board design used to derive this data was a 3-inch × 3-inch, two layer board with 2 ounce copper traces on top

of the board.

(2)

The JEDEC high K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1 ounce internal power and

ground planes and 2 ounce copper traces on top and bottom of the board.

2

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