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MAX5121BEEE Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX5121BEEE Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 20 page  +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference 4 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS—MAX5121 (+3V) (continued) (VDD = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) To ±0.5LSB, VSTEP = 2V CS = VDD, fSCLK = 100kHz, VSCLK = 3Vp-p CONDITIONS µA 320 ISHDN Power-Supply Current in Shutdown µA 500 600 IDD Power-Supply Current (Note 5) V 2.7 3.6 VDD Power-Supply Voltage (Note 5) nV-s 5 Digital Feedthrough ms 2 Time Required to Exit Shutdown k Ω 83 121 ROS OS Input Resistance µs 20 Output Settling Time V 0 to VDD Output Voltage Swing (Note 4) UNITS MIN TYP MAX SYMBOL PARAMETER ISINK = 2mA V 0.13 0.4 VOL Output Low Voltage ISOURCE = 2mA V VDD - 0.5 VOH Output High Voltage VIN = 0 or VDD µA -1 0.001 1 IIN Input Leakage Current pF 8 CIN Input Capacitance V/µs 0.6 SR Voltage Output Slew Rate TIMING CHARACTERISTICS—MAX5120 (+5V) (VDD = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) ns 40 tCSS CS Fall to SCLK Rise Setup Time ns 40 tCL SCLK Pulse Width Low CONDITIONS ns 100 tCP SCLK Clock Period ns 40 tCH SCLK Pulse Width High ns 0 tCSH SCLK Rise to CS Rise Hold Time ns 10 tCS0 SCLK Rise to CS Fall Delay Time ns 40 tDS SDI Setup Time ns 0 tDH SDI Hold Time UNITS MIN TYP MAX SYMBOL PARAMETER ns 100 tCSW CS Pulse Width High ns 40 tCS1 CS Rise to SCLK Rise Hold Time CLOAD = 200pF ns 80 tDO1 SCLK Rise to DOUT Valid Propagation Delay Time CLOAD = 200pF ns 80 tDO2 SCLK Fall to DOUT Valid Propagation Delay Time DIGITAL OUTPUTS POWER REQUIREMENTS DYNAMIC PERFORMANCE |
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