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MAX5176BEEE Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX5176BEEE Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 16 page ![]() Low-Power, Serial, 12-Bit DACs with Voltage Output _______________________________________________________________________________________ 5 Note 1: INL guaranteed between codes 10 and 4095. Note 2: Offset is measured at the code that comes closest to 10mV. Note 3: Accuracy is better than 1 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points. Note 4: RL = open and digital inputs are either VDD or DGND. Note 5: INL guaranteed between codes 20 and 4095. ELECTRICAL CHARACTERISTICS—MAX5176 (continued) (VDD = +2.7V to +3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C). Power-Supply Current (Note 4) IDD 0.35 0.4 mA Positive Supply Voltage VDD 2.7 3.6 V Digital Feedthrough 1 nV-s CS = VDD, DIN = 50kHz; fSCLK = 100kHz, VSCLK = 3Vp-p PARAMETER SYMBOL MIN TYP MAX UNITS Time Required to Exit Shutdown 40 µs OS Pin Input Resistance 80 120 k Ω Output Voltage Swing (Note 3) 0 VDD V Voltage Output Slew Rate SR 0.6 V/µs CS Pulse Width High tCSW 150 ns SCLK Rise to CS Fall Delay tCS0 10 ns Output Settling Time 18 µs To ±0.5LSB, from 10mV to full-scale SCLK Fall to DOUT Valid Propagation Delay tDO2 200 ns CLOAD = 200pF CS Rise to SCLK Rise Hold Time tCS1 75 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 200 ns CLOAD = 200pF SDI Hold Time tDH 0 ns SDI Setup Time tDS 60 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CSB Fall to SCLK Rise Setup Time tCSS 60 ns SCLK Pulse Width Low tCL CONDITIONS 75 ns SCLK Pulse Width High tCH 75 ns SCLK Clock Period tCP 150 ns Shutdown Current (Note 4) 110 µA DYNAMIC PERFORMANCE POWER SUPPLIES TIMING CHARACTERISTICS |
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