The inputs of unused drivers may be left unconnected

because they have internal 400k

the internal pull-ups.

EIA/TIA-562 and EIA/TIA-232 Receivers

The MAX563’s receivers convert ±3.7V to ±13.2V

EIA/TIA-562 signal levels into +3V logic levels; they are

rated to receive signals up to ±25V to accommodate

EIA/TIA-232 signals as well. Both receivers invert. Their

inputs are each equipped with an internal 5k

Ω (nomi-

nal) terminating resistor connected to ground, and the

input logic thresholds are 0.4V and 2.4V. The positive

remain high whenever their inputs are left open.

The receivers are active when

EN is low, and have

high-impedance outputs when

EN is high.

When

SHDN is high, the receivers have hysteresis.

This produces clean output transitions, even with slow-

moving input signals that exhibit moderate amounts of

noise and ringing. When shut down, the receivers have

no hysteresis, and the propagation delay increases.

Shutdown and Enable Control

The

SHDN and EN controls are independent. Both

receivers are always active when

EN is low. With EN

low and

SHDN high, the receivers operate at full speed

and have hysteresis. When active in shutdown mode

(

EN = SHDN = low), the receivers operate at reduced

power and speed, and without hysteresis.

The charge pumps and transmitters operate only when

SHDN is high; they are unaffected by EN. When shut

down (

transmitter outputs are high impedance if they are

backdriven with voltages not exceeding ±15V. The pull-

up resistors at the driver inputs are disconnected in

shutdown mode to save power. During shutdown, V+ is

_______________________________________________________________________________________

5

+3.3V-Powered, EIA/TIA-562 Dual Transceiver

with Receivers Active in Shutdown

V+

GND

MAX563

0.1µF

0.1µF

R1 & R2

T1 & T2

0.1µF

C1+

C1-

C2+

C2-

+3.6V

400k

5k

0V +3.6V

DRIVE

0.1µF

0.1µF

3k

+3.6V

EN

SHDN

V-

+3.6V

V+

OV

V-

OV

INPUT

OUTPUT

+3V

INPUT

OUTPUT

50%

50%

+3V

50%

50%

GND

0V

Figure 1. Shutdown Current Test Circuit

Figure 2. Transmitter Propagation Delay Timing

Figure 3. Receiver Propagation Delay Timing