MAX769 datasheet(3/16 Pages) MAXIM

3 / 16 page

2 or 3-Cell, Step-Up/Down,

Two-Way Pager System IC

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ELECTRICAL CHARACTERISTICS (continued)

(OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

-3.5

3.5

OUT Error, Coast Mode

(Note 11)

Coast Mode, OUT = 1.8V to 4.9V

-3.5

3.5

OUT Error, Run Mode (Note 12)

Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V

Run Mode, OUT = 1.8V to 4.9V

Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V

CONDITIONS

BATT = 1.6V to 4.5V

OUT Line Regulation

IOUT = 80mA, COUT = 47µF with ESR < 0.25Ω

mVp-p

OUT Voltage Ripple

LX1, LX2, BATT = 3.0V

Ω

0.9

1.8

LX On-Resistance (Note 14)

CS to SCL Hold Time (tCSH)

CS to SCL Setup Time (tCSS)

100

SDI Setup Time (tDS)

NMOS

PMOS

1.3

2.6

TA = +25°C, FILT connected to REF

kHz

210

270

325

Frequency, Free-Run

Backup Mode, NICD = 3.3V

fSYNC = 38.4kHz

100

kHz

CS Pulse Width High (tCSW)

268.8

Frequency, Locked

CS to SDO Disable (tTR)

Ω

fSYNC = 38.4kHz, FILT Network = 1nF

 (22nF + 10kΩ)

kHz

±15

Jitter (Note 15)

fSYNC = 38.4kHz, FILT Network = 1nF

 (22nF + 10kΩ)

Capture Time (Note 15)

Backup-Regulator

On-Resistance (Note 16)

0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1

SCL Pulse Width High or Low

(tCH, tCL)

115

Output Current, Run Mode

(Note 10)

Current High

Output Current, Coast Mode

(Note 10)

UNITS

MIN

TYP

MAX

PARAMETER

0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1

0.45

1.5

Current Low

OUT = 2.8V, IOUT = 20mA, NICD = 3.3V

-3.5

3.5

OUT Error, Backup Regulator

50% duty cycle

MHz

SCL Maximum Clock Rate

OUT = 3.0V

Maximum LX Duty Cycle

During the inductor charge cycle

300

350

400

LX Switch Current Limit

CS to SDO Output Valid (tDV)

SCL to SDO Output Valid (tDO)

SDI Hold Time (tDH)

IOUT = 1mA to 80mA, Run Mode

OUT Load Regulation

Coast or Run Mode, OUT = 1.8V to 4.9V

100

170

OUT DAC Step Size (Note 13)

SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9)

DC-DC CONVERTER

PHASE-LOCKED LOOP (PLL)

NICD CHARGER

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