VCC

GND

RT

EN

COMP

FB

VIN

SW

1

4

3

2

8

5

7

6

1

4

3

5

8

7

6

EP

SW

VIN

EN

COMP

VCC

FB

RT

GND

2

LM5002

SNVS496D – JANUARY 2007 – REVISED MARCH 2013

www.ti.com

Connection Diagram

Figure 2. SOIC-8 Package

Figure 3. WSON-8 Package

Top View

Top View

PIN DESCRIPTIONS

Pin

Name

Description

Application Information

SOIC

WSON

1

3

SW

Switch pin

The drain terminal of the internal power MOSFET.

2

4

VIN

Input supply pin

Nominal operating range: 3.1V to 75V.

VCC tracks VIN up to 6.9V. Above VIN = 6.9V, VCC is

regulated to 6.9 Volts. A 0.47 µF or greater ceramic

Bias regulator output, or input for external

decoupling capacitor is required. An external voltage (7V –

3

5

VCC

bias supply

12V) can be applied to this pin which disables the internal

VCC regulator to reduce internal power dissipation and

improve converter efficiency.

Internal reference for the regulator control functions and the

4

6

GND

Ground

power MOSFET current sense resistor connection.

The internal oscillator is set with a resistor, between this pin

and the GND pin. The recommended frequency range is

Oscillator frequency programming and

50KHz to 1.5 MHz. The RT pin can accept synchronization

5

7

RT

optional synchronization pulse input

pulses from an external clock. A 100 pF capacitor is

recommended for coupling the synchronizing clock to the

RT pin.

This pin is connected to the inverting input of the internal

Feedback input from the regulated output

6

8

FB

error amplifier. The 1.26V reference is internally connected

voltage

to the non-inverting input of the error amplifier.

The loop compensation network should be connected

between the COMP pin and the FB pin. COMP pull-up is

Open drain output of the internal error

7

1

COMP

provided by an internal 5 k

Ω resistor which may be used to

amplifier

bias an opto-coupler transistor (while FB is grounded) for

isolated ground applications.

An external voltage divider can be used to set the line

Enable / Under Voltage Lock-Out /

undervoltage lockout threshold. If the EN pin is left

8

2

EN

Shutdown input

unconnected, a 6 µA pull-up current source pulls the EN pin

high to enable the regulator.

Exposed metal pad on the underside of the package with a

resistive connection to pin 6. It is recommended to connect

NA

EP

EP

Exposed Pad, WSON only

this pad to the PC board ground plane in order to improve

heat dissipation.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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