3

P/N:PM0344

REV. 1.4, JUL. 16, 2001

MX23L4100

AC Test Conditions

Input Pulse Levels

0.4V~2.4V

Input Rise and Fall Times

10ns

Input Timing Level

1.4V

Output Timing Level

1.4V

Output Load

See Figure

AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)

Item

Symbol

23L4100-10

23L4100-12

23L4100-15

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

tRC

100ns

-

120ns

-

150ns

-

Address Access Time

tAA

-

100ns

-

120ns

-

150ns

Chip Enable Access Time

tACE

-

100ns

-

120ns

-

150ns

Output Enable Time

tOE

-

50ns

-

60ns

-

70ns

Output Hold After Address

tOH

-

0ns

-

0ns

-

0ns

Output High Z Delay

tHZ

-

20ns

-

20ns

-

20ns

Note:Output high-impedance delay (tHZ) is measured

from OE or CE going high, and this parameter guaran-

teed by design over the full voltage and temperature op-

erating range - not tested.

Note:No output loading is present in tester load board.

Active loading is used and under software programming control.

Output loading capacitance includes load board's and all stray capacitance.

DOUT

C<100pF

IOL (load)=1.6mA

IOH (load)=-0.4mA

TIMING DIAGRAM

ACCESS TIMING

tACE

tAA

tOH

tHZ

ADD

ADD

ADD

ADD

CE

OE

DATA

VALID

VALID

VALID

tRC

tOE