BLOCK DIAGRAM

D

R

E

D

R

E

D

R

E

D

R

E

D

R

E

D

R

E

MR

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

s Max. toggle frequency of 700MHz

s Clock to Q max. of 1200ps

s Industry standard 100K ECL levels

s Extended supply voltage option:

s Voltage and temperature compensation for improved

noise immunity

s Internal 75K

s 50% faster than Fairchild 300K

s Better than 20% lower power than Fairchild

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

FEATURES

HEX D FLIP-FLOP

SY100S351

DESCRIPTION

The SY100S351 offers six D-type, edge-triggered,

master/slave flip-flops with differential outputs, and is

designed for use in high-performance ECL systems. The

flip-flops are controlled by the signal from the logical OR

go to a logic HIGH. The Master Reset (MR) input overrides

all other inputs and takes the Q outputs to a logic LOW. The

inputs on this device have 75K

Ω pull-down resistors.

Rev.: G

Amendment: /0

Issue Date:

July, 1999

18

17

16

15

14

13

1

2

3

4

5

6

7

24

8

23

9

22

10

21

11

20

12

19

Top View

Flatpack

F24-1

MR

4

3

2

1

28

27

12

13

14

15

16

17

19

11

20

10

21

9

22

8

23

7

24

6

Top View

PLCC

J28-1

26

18

25

5

PIN CONFIGURATIONS

1