QUAD

MULTIPLEXER/LATCH

SY100S355

FEATURES

s Max. propagation delay of 1100ps

s Max. enable to output delay of 1400ps

s Industry standard 100K ECL levels

s Extended supply voltage option:

s Voltage and temperature compensation for improved

noise immunity

s Internal 75K

s 50% faster than Fairchild

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

DESCRIPTION

The SY100S355 offers four transparent latches with

differential outputs and is designed for use in high-

latch. The Select inputs can also force the outputs to a logic

LOW when the latch is in the transparent mode. The

latches are in the transparent mode when both Enables

If the Select inputs are tied together, then input data from

either Enable input will latch the outputs with the most

recent data at the latch inputs being stored. The Master

Reset (MR) input overrides all other inputs and takes the Q

outputs to a logic LOW. The inputs on this device have

75K

Ω pull-down resistors.

Rev.: G

Amendment: /0

Issue Date:

July, 1999

PIN CONFIGURATIONS

BLOCK DIAGRAM

D

CD

E

Q

D

CD

E

Q

D

CD

E

Q

D

CD

E

Q

MR

18

17

16

15

14

13

1

2

3

4

5

6

7

24

8

23

9

22

10

21

11

20

12

19

Top View

Flatpack

F24-1

MR

4

3

2

1

28

27

12

13

14

15

16

17

19

11

20

10

21

9

22

8

23

7

24

6

Top View

PLCC

J28-1

26

18

25

5

1