24LCS61 datasheet(12/16 Pages) MICROCHIP

12 / 16 page

24LCS61/62

DS21226A-page 12

Preliminary

8.0

READ OPERATIONS

Read operations are initiated in a similar way as the

write operations. There are three basic types of read

operations: current address read, random read, and

sequential read.

8.1

Current Address Read

The 24LCS61/62 contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

read access was to address n, the next current address

read operation would access data from address n + 1.

Upon receipt of the correct control byte and ID byte, the

24LCS61/62 issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer but does generate a stop condition and the

24LCS61/62 discontinues transmission (Figure 8-1).

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set. This is done by sending the word address to the

24LCS61/62 as part of a write operation. After the ID

byte and word address are sent, the master generates

a start condition following the acknowledge. This termi-

nates the write operation, but not before the internal

address pointer is set. Then the master sends the con-

trol byte and ID byte for a read command. The

24LCS61/62 will then issue an acknowledge and trans-

mits the eight bit data word. The master will not

acknowledge the transfer but does generate a stop

condition and the 24LCS61/62 discontinues transmis-

sion (Figure 8-2).

8.3

Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24LCS61/62 transmits

the ﬁrst data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24LCS61/62 to transmit the next sequen-

tially addressed 8-bit word (Figure 8-3).

To provide sequential reads the 24LCS61/62 contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation. The internal address pointer

will

automatically

roll

over

from

address

7Fh

(24LCS61) or FFh (24LCS62) to address 00h.

FIGURE 8-1:

CURRENT ADDRESS READ

FIGURE 8-2:

RANDOM READ

FIGURE 8-3:

SEQUENTIAL READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA

DEVICE

ID BYTE

10 O 00 1

OE Bit = EDS Pin Output Enable; see Section 9.0

CONTROL

BYTE

ADDRESS

BYTE

CONTROL

BYTE

DATA

BYTE

DEVICE

ID BYTE

DEVICE

ID BYTE

10 O 010

01 0 O 00 1

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

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