24LC62-IP datasheet(10/16 Pages) MICROCHIP

10 / 16 page

24LCS61/62

DS21226A-page 10

Preliminary

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the start signal from the master, the control

byte for a write command is sent by the master trans-

mitter. The device will acknowledge this control byte

during the ninth clock pulse. The next byte transmitted

by the master is the ID byte for the device. After receiv-

ing another acknowledge signal from the 24LCS61/62,

the master device will transmit the address and then

the data word to be written into the addressed memory

location. The 24LCS61/62 acknowledges between

each byte, and the master then generates a stop con-

dition. This initiates the internal write cycle, and during

this time the 24LCS61/62 will not generate acknowl-

edge signals (Figure 6-1).

6.2

Page Write

The control byte, ID byte, word address, and the ﬁrst

data byte are transmitted to the 24LCS61/62 in the

same way as in a byte write. But, instead of generating

a stop condition, the master transmits up to 15 addi-

tional data bytes to the 24LCS61/62, which are tempo-

rarily stored in the on-chip page buffer and will be

written into the memory after the master has transmit-

ted a stop condition. If the master should transmit more

than 16 bytes prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 6-2) and the 24LCS61/

62 will not generate acknowledge.

6.3

Low Voltage Write Protection

The 24LCS61/62 employs a VCC threshold detector cir-

cuit which disables the internal erase/write logic, if the

VCC is below 1.5 volts at nominal conditions.

6.4

Set Write Protection Command

The Set Write Protection command allows the user to

write protect a portion of the array. For the 24LCS61

this command will write protect the entire array. For the

24LCS62 this command will protect the lower half of

the array. This command is illustrated in Figure 6-3.

This is a one time only command and cannot be

reversed once the protection fuse has been set.

Once the Write protect feature has been set, the device

will no longer acknowledge the control byte (or any of

the other bytes) of this command. The STOP bit of this

command initiates an internal write cycle, and during

this time the 24LCS61/62 will not generate acknowl-

edge signals.

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

FIGURE 6-3:

SET WRITE PROTECTION COMMAND

DEVICE

ID BYTE

DATA

CONTROL

BYTE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

ADDRESS

BYTE

01 0 O 010

OE Bit = EDS Pin Output Enable; see Section 9.0

CONTROL

BYTE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

ADDRESS

BYTE

DATA BYTE 0

DATA BYTE 15

DEVICE

ID BYTE

01 0

0 1 0

CONTROL

BYTE

01 0

XXXXXXXX

DEVICE

ID BYTE

ADDRESS

BYTE

DATA BYTE

24LC62-IP Datasheet(PDF) 10 Page - Microchip Technology

24LC62-IP Datasheet(HTML) 10 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL