Electronic Components Datasheet Search
  English  ▼

X  

TLE7231G Datasheet(PDF) 12 Page - Infineon Technologies AG

Part # TLE7231G
Description  4 channel low-side driver
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE7231G Datasheet(HTML) 12 Page - Infineon Technologies AG

Back Button TLE7231G Datasheet HTML 8Page - Infineon Technologies AG TLE7231G Datasheet HTML 9Page - Infineon Technologies AG TLE7231G Datasheet HTML 10Page - Infineon Technologies AG TLE7231G Datasheet HTML 11Page - Infineon Technologies AG TLE7231G Datasheet HTML 12Page - Infineon Technologies AG TLE7231G Datasheet HTML 13Page - Infineon Technologies AG TLE7231G Datasheet HTML 14Page - Infineon Technologies AG TLE7231G Datasheet HTML 15Page - Infineon Technologies AG TLE7231G Datasheet HTML 16Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 30 page
background image
SPI Driver for Enhanced Relay Control
SPIDER - TLE7231G
Power Stages
Datasheet
12
Rev. 1.2, 2014-05-09
6
Power Stages
The TLE7231G is a four channel low-side relay switch.
The power stages are made of N-channel vertical power MOSFET transistors.
6.1
Input Circuit
The TLE7231G has an input pin, that can be configured to be used for control of the output stages. The INn
parameter of the SPI provide the following operation modes:
•
channel is in off mode without diagnosis
(if all channels are programmed to this mode, the device goes into idle mode)
•
channel is switched according to signal level at input pin IN
•
channel is switched on
•
channel is switched off with active diagnosis
Figure 4 shows the input circuit of TLE7231G.
Figure 4
Input Multiplexer
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode.
6.2
Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to
V
DS(CL) potential, because the inductance
intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device,
see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited.
Figure 5
Output Clamp Implementation
Channel 3
Channel 2
Channel 1
IN
I
IN
Channel 0
1
IN0
InputLogic.emf
0
0
D0
&
OutputClamp.emf
VBAT
ID
VDS(CL)
OUT
V
DS
GND
L,
R
L



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com