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PIC17C752 Datasheet(PDF) 160 Page - Microchip Technology |
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PIC17C752 Datasheet(HTML) 160 Page - Microchip Technology |
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160 / 320 page ![]() PIC17C75X DS30264A-page 160 Preliminary © 1997 Microchip Technology Inc. 15.2.14 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its IDLE state. (Figure 15-37). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user ser- vices the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communica- tion by asserting a START condition. If a START, RESTART, STOP, or Acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- vices the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communica- tion by asserting a START condition. The Master will continue to monitor the SDA and SCL pins, and if a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when bus collision occurred. In multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. FIGURE 15-37: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA SCL BCLIF SDA released SDA line pulled low by another source Sample SDA. While SCL is high data doesn’t match what is driven Bus collision has occurred. Set bus collision interrupt. by the master. by master Data changes while SCL = 0 |
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