TC835CBU datasheet(13/24 Pages) MICROCHIP

13 / 24 page

DS21478B-page 13

TC835

Smaller or cheaper capacitors can be used if accurate

readings are not required for the first few seconds of

recovery.

6.1.3

REFERENCE VOLTAGE

The analog input required to generate a full scale out-

put is VIN =2VREF.

The stability of the reference voltage is a major factor in

the overall absolute accuracy of the converter. For this

reason, it is recommended that a high-quality reference

be used where high-accuracy absolute measurements

are being made.

6.2

Conversion Timing

6.2.1

LINE FREQUENCY REJECTION

A signal integration period at a multiple of the 60Hz line

frequency will maximize 60Hz "line noise" rejection. A

200kHz clock frequency will reject 60Hz and 400Hz

noise. This corresponds to five readings per second

(see Table 6-1 and Table 6-2).

TABLE 6-1:

CONVERSION RATE VS.

CLOCK FREQUENCY

TABLE 6-2:

LINE FREQUENCY VS.

CLOCK FREQUENCY

The conversion rate is easily calculated:

EQUATION 6-3:

6.3

Power Supplies and Grounds

6.3.1

POWER SUPPLIES

The TC835 is designed to work from ±5V supplies. For

single +5V operation, a TC7660 can provide a

–5V supply.

6.3.2

GROUNDING

Systems should use separate digital and analog

ground systems to avoid loss of accuracy.

6.4

High-Speed Operation

The maximum conversion rate of most dual-slope A/D

converters is limited by the frequency response of the

comparator. The comparator in this circuit follows the

integrator ramp with a 3

µsec delay, and at a clock fre-

quency of 200kHz (5

µsec period), half of the first refer-

ence integrate clock period is lost in delay. This means

that the meter reading will change from 0 to 1 with a

µV input, 1 to 2 with 150µV, 2to3 at 250µV, etc. This

transition at midpoint is considered desirable by most

users, however, if the clock frequency is increased

appreciably above 200kHz, the instrument will flash "1"

on noise peaks even when the input is shorted.

For many dedicated applications where the input signal

is always of one polarity, the delay of the comparator

need not be a limitation. Since the nonlinearity and

noise do not increase substantially with frequency,

clock rates of up to ~1MHz may be used. For a fixed

clock frequency, the extra count or counts caused by

comparator delay will be a constant and can be

subtracted out digitally.

The clock frequency may be extended above 200kHz

without this error, however, by using a low-value resis-

tor in series with the integrating capacitor. The effect of

the resistor is to introduce a small pedestal voltage onto

the integrator output at the beginning of the reference

integrate phase. By careful selection of the ratio

between this resistor and the integrating resistor (a few

tens of ohms in the recommended circuit), the compar-

ator delay can be compensated and the maximum

clock frequency extended by approximately a factor of

3. At higher frequencies, ringing and second-order

breaks will cause significant nonlinearities in the first

few counts of the instrument.

The minimum clock frequency is established by leak-

age on the auto zero and reference capacitors. With

most devices, measurement cycles as long as 10 sec-

onds give no measurable leakage error.

Oscillator Frequency

(kHz)

Conversion Rate

(Conv./Sec.)

100

2.5

120

200

300

7.5

400

800

1200

Oscillator Frequency

(kHz)

Line Frequency Rejection

60Hz

50Hz

400Hz

50.000

•

53.333

—

•

66.667

•

—

•

80.000

—

•

83.333

—

•

100.000

•

125.000

—

•

133.333

—

•

166.667

—

•

200.000

•

—

•

250.000

Reading 1/sec =

Clock Frequency (Hz)

4000

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