LM3280

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SNOSAU4B – OCTOBER 2006 – REVISED FEBRUARY 2013

INTERNAL SYNCHRONOUS RECTIFICATION

While in PWM mode, the buck converter uses an internal NFET as a synchronous rectifier to reduce rectifier

forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

With medium and heavy loads, the internal NFET synchronous rectifier is turned on during the inductor current

down slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. There

is no zero cross detect, which means that the NFET can conduct current in both directions and inductor current is

always continuous. The advantage of this method is that the part remains in PWM mode at light loads or no load

conditions. The NFET has a current limit. The NFET is designed to conduct through its intrinsic body diode

during transient intervals before it turns on, eliminating the need for an external diode.

CURRENT LIMITING

A current limit feature allows the buck converter to protect itself and external components during overload

conditions. In PWM mode, a 940mA (max.) cycle-by-cycle current limit is normally used. If an excessive load

pulls the output voltage down to below approximately 0.375V, indicating a possible short to ground, then the

device switches to a timed current limit mode. In timed current limit mode, the internal PFET switch is turned off

after the current comparator trips, and the beginning of the next cycle is inhibited for 3.5µs to force the

instantaneous inductor current to ramp down to a safe value. After the 3.5µs interval, the internal PFET is turned

on again. This cycle is repeated until the load is reduced and the output voltage exceeds approximately 0.375V.

Therefore, the device may not startup if an excessive load is connected to the output when the device is enabled.

The synchronous rectifier is off in the timed current limit mode. Timed current limit prevents the loss of current

control seen in some products when the output voltage is pulled low in serious overload conditions.

A current limit is also provided for the NFET. This is approximately

−500mA. Both the NFET and the PFET are

turned off in negative current limit until the PFET is turned on again at the beginning of the next cycle. The

negative current limit inhibits buildup of excessive negative inductor current.

In the Bypass mode, the bypass current limit is 1000mA (typ.). The output voltage drops when the bypass

current limit kicks in.

LDO

LDO OPERATION

The LDO provides a nominal output voltage of 2.85V. Each LDO can be enabled when the respective enable pin

is set high (>1.2V) after the buck converter has been enabled. The LDO will automatically be disabled whenever

occur between disabled one LDO and enabling another. Otherwise, all LDOs are disabled.

CHARGE AND DISCHARGE

Each LDO includes an active charge circuit. 7.5us (typ.) after the LDO is enabled, the current limit of the LDO is

set to 60mA. A 1µF load capacitor will be charged to 90% of the nominal output voltage in approximately 50us

(typ.). (Note: This number is based on the assumption that the PWM loop has been enabled and given time to

stabilize before the LDO is enabled.) The current limit is then reduced to 40mA.

An internal pull-down resistor is also included in each LDO. The LDO discharges the output capacitor through the

pull-down resistor when LDO is disabled.

Shutdown Mode

shutdown, the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of

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