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AR0141 Datasheet(PDF) 13 Page - ON Semiconductor |
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AR0141 Datasheet(HTML) 13 Page - ON Semiconductor |
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13 / 63 page ![]() AR0141CS DS Rev. D Pub. 6/15 EN 13 ©Semiconductor Components Industries, LLC, 2015. AR0141CS: 1/4-Inch Digital Image Sensor Pixel Output Interfaces Pixel Output Interfaces Parallel Interface The parallel pixel data interface uses these output-only signals: •FRAME_VALID •LINE_VALID •PIXCLK •DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 5 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchro- nously between the driven and High-Z under pin or register control, as shown in Table 4. Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 5. Table 4: Output Enable Control OE_BAR Pin Drive Pins R0x301A[6] Description Disabled 0 Interface High-Z Disabled 1 Interface driven 1 0 Interface High-Z X1 Interface driven 0X Interface driven Table 5: Configuration of the Pixel Data Interface Serializer Disable R0x301 A[12] Parallel Enable R0x301 A[7] Description 0 0 Power up default. Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface. |
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