SN74LS168

http://onsemi.com

3

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

Supply Voltage

54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

Operating Ambient Temperature Range

54

74

−55

0

25

25

125

70

°C

Output Current — High

54, 74

−0.4

mA

Output Current — Low

54

74

4.0

8.0

mA

Symbol

Parameter

Limits

Unit

Test Conditions

Min

Typ

Max

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

All Inputs

74

0.8

Input Clamp Diode Voltage

−0.65

−1.5

V

Output HIGH Voltage

54

2.5

3.5

V

74

2.7

3.5

V

Output LOW Voltage

54, 74

0.25

0.4

V

per Truth Table

74

0.35

0.5

V

Input HIGH Current

Other Inputs

CET Input

20

40

μA

Other Input

CET Input

0.1

0.2

mA

Input LOW Current

Other Input

CET Input

−0.4

−0.8

mA

Short Circuit Current (Note 1)

−20

−100

mA

Power Supply Current

34

mA

Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.

FUNCTIONAL DESCRIPTION

The SN54/74LS168 uses edge-triggered D-type flip-flops

that have no constraints on changing the control or data input

signals in either state of the Clock. The only requirement is

that the various inputs attain the desired state at least a

set-up time before the rising edge of the clock and remain

valid for the recommended hold time thereafter.

The parallel load operation takes precedence over the

other operations, as indicated in the Mode Select Table.

flip-flops on the next rising edge of the Clock. In order for

counting to occur, both CEP and CET must be LOW and PE

must be HIGH. The U/D input then determines the direction

of counting.

The Terminal Count (TC) output is normally HIGH and

goes LOW, provided that CET is LOW, when a counter

reaches zero in the COUNT DOWN mode or reaches 15 (9

for the SN54/74LS168) in the COUNT UP mode. The TC

output state is not a function of the Count Enable Parallel

(CEP) input level. The TC output of the SN54/74LS168

decade counter can also be LOW in the illegal states 11, 13

and 15, which can occur when power is turned on or via

parallel loading. If illegal state occurs, the SN54/74LS168 will

return to the legitimate sequence within two counts. Since

the TC signal is derived by decoding the flip-flop states, there

exists the possibility of decoding spikes on TC. For this

reason the use of TC as a clock signal is not recommended.