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ROSC

ROSC

TPS65279

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Selection

TPS65279

www.ti.com

SLVSC85C – AUGUST 2013 – REVISED MAY 2015

Feature Description (continued)

8.3.2.1 Synchronization

An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1600

kHz, and to easily switch from Resistor mode to Synchronization mode.

To implement the synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle

between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start

of the switching cycle is synchronized to the falling edge of ROSC pin.

In applications where both Resistor mode and Synchronization mode are needed, the device can be configured

as shown in Figure 17. Before the external clock is present, the device works in Resistor mode and the switching

frequency is set by ROSC resistor. When the external clock is present, the Synchronization mode overrides the

Resistor mode. The first time the ROSC pin is pulled above the ROSC high threshold (2 V), the device switches

from the Resistor mode to the Synchronization mode and the ROSC pin becomes high impedance as the PLL

starts to lock onto the frequency of the external clock. It is not recommended to switch from the Synchronization

mode back to the Resistor mode because the internal switching frequency drops to 100 kHz first before returning

to the switching frequency set by ROSC resistor.

Figure 17. Resistor Mode and Synchronization Mode

8.3.3 Soft-Start Time

The start-up of buck output is controlled by the voltage on the respective SS pin. When the voltage on the SS pin

is less than the internal 0.6-V reference, the TPS65279 regulates the internal feedback voltage to the voltage on

the SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output

of buck to track another supply during start-up. The device has an internal pullup current source of 6 µA that

charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The TPS65279 regulates

the internal feedback voltage according to the voltage on the SS pin, allowing VOUT to rise smoothly from 0 V to

its final regulated voltage. The total soft-start time will be calculated approximately:

(1)

8.3.4 Out-of-Phase Operation

In order to reduce input ripple current, Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system

having less input ripple, then to lower component cost, save board space and reduce EMI.

8.3.5 Output Overvoltage Protection (OVP)

The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For

example, when the power supply output is overloaded the error amplifier compares the actual output voltage to

the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable

time, the output of the error amplifier demands maximum output current. Once the condition is removed, the

regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications

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