ERROR

AMP

SS

FB

40k

100k

0.75V

60k

R1

R2

R3

C2

C1

PWM

COMP

CV

No Lead

Network

Required

LM5115

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SNVS343E – MARCH 2005 – REVISED MARCH 2013

Injecting a signal proportional to the instantaneous inductor current into a voltage mode controller improves the

control loop stability and bandwidth. This current injection eliminates the lead R-C lead network in the feedback

path that is normally required with voltage mode control (see Figure 18). Eliminating the lead network not only

simplifies the compensation, but also reduces sensitivity to output noise that could pass through the lead network

to the error amplifier.

The design of the voltage feedback path through the error amp begins with the selection of R1 and R2 in

Figure 18 to set the regulated output voltage. The steady state output voltage after soft-start is determined by the

following equation:

VOUT(final) = 0.75V x (1+R1/R2)

(4)

The parallel impedance of the R1, R2 resistor divider should be approximately 2k

Ω (between 0.5kΩ and 5kΩ).

Lower resistance values may not be properly driven by the error amplifier output and higher feedback resistances

can introduce noise sensitivity. The next step in the design process is selection of R3, which sets the ac gain of

the error amplifier. The ac gain is given by the following equation and should be set to a value less than 30.

GAIN(ac) = R3/(R1|| R2) < 30

(5)

The capacitor C1 is connected in series with R3 to increase the dc gain of the voltage regulation loop and

improve output voltage accuracy. The corner frequency set by R3 x C1 should be less than 1/10th of the cross-

over frequency of the overall converter such that capacitor C1 does not add phase lag at the crossover

frequency. Capacitor C2 is added to reduce the noise in the voltage control loop. The value of C2 should be less

than 500pF and C2 may not be necessary with very careful PC board layout.

Figure 18. Voltage Sensing and Feedback

Current Limiting (CS, CO and VOUT)

Current limiting is implemented through the current sense amplifier as illustrated in Figure 17. The current sense

amplifier monitors the inductor current that flows through a sense resistor connected between CS and VOUT.

The voltage gain of the current sense amplifier is nominally equal to 16. The output of current sense signal is

shifted by 1.27V to produce the internal CV reference signal. The CV signal drives a current limit amplifier with

nominal transconductance of 16mA/V. The current limit amplifier has an open drain (sink only) output stage and

its output pin CO is typically connected to the COMP pin. During normal operation, the voltage error amplifier

controls the COMP pin voltage which adjusts the PWM duty cycle by varying the internal CRMIX level

down on COMP through the CO pin. Pulling COMP low reduces the CRMIX signal below the CV signal level.

When CRMIX does not exceed the CV signal, the PWM comparator inhibits output pulses until the CRMIX signal

increases to a normal operating level.

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