LM25115MTSLASHNOPB datasheet(2/23 Pages) TI

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VBIAS

PGND

VCC

AGND

VOUT

RAMP

SYNC

COMP

LM25115

SNVS418A – NOVEMBER 2005 – REVISED APRIL 2013

www.ti.com

Connection Diagram

Figure 2. 16-Lead TSSOP, WSON

See Package Numbers PW0016A and NHQ0016A

PIN DESCRIPTIONS

Name

Description

Application Information

Current Sense amplifier positive input

A low inductance current sense resistor is connected between CS

and VOUT. Current limiting occurs when the differential voltage

between CS and VOUT exceeds 45mV (typical).

VOUT

Current sense amplifier negative input

Connected directly to the output voltage. The current sense

amplifier operates over a voltage range from 0V to 13.5V at the

VOUT pin.

AGND

Analog ground

Connect directly to the power ground pin (PGND).

Current limit output

For normal current limit operation, connect the CO pin to the

COMP pin. Leave this pin open to disable the current limit function.

COMP

Compensation. Error amplifier output

COMP pin pull-up is provided by an internal 300uA current source.

Feedback. Error amplifier inverting input

Connected to the regulated output through the feedback resistor

divider and compensation components. The non-inverting input of

the error amplifier is internally connected to the SS pin.

Soft-start control

An external capacitor and the equivalent impedance of an internal

resistor divider connected to the bandgap voltage reference set the

soft-start time. The steady state operating voltage of the SS pin

equal to 0.75V (typical).

RAMP

PWM Ramp signal

An external capacitor connected to this pin sets the ramp slope for

the voltage mode PWM. The RAMP capacitor is charged with a

current that is proportional to current into the SYNC pin. The

capacitor is discharged at the end of every cycle by an internal

MOSFET.

SYNC

Synchronization input

A low impedance current input pin. The current into this pin sets the

RAMP capacitor charge current and the frequency of an internal

oscillator that provides a clock for the free-run (DC input) mode .

PGND

Power Ground

Connect directly to the analog ground pin (AGND).

Low side gate driver output

Connect to the gate of the low side synchronous MOSFET through

a short, low inductance path.

VCC

Output of bias regulator

Nominal 7V output from the internal LDO bias regulator. Locally

decouple to PGND using a low ESR/ESL capacitor located as

close to controller as possible.

High side MOSFET source connection

Connect to negative terminal of the bootstrap capacitor and the

source terminal of the high side MOSFET.

High side gate driver output

Connect to the gate of high side MOSFET through a short, low

inductance path.

High side gate driver bootstrap rail

Connect to the cathode of the bootstrap diode and the positive

terminal of the bootstrap capacitor. The bootstrap capacitor

supplies current to charge the high side MOSFET gate and should

be placed as close to controller as possible.

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