SM5165AV

NIPPON PRECISION CIRCUITS—2

BLOCK DIAGRAM

PIN DESCRIPTION

Number

Name

I/O

Description

1

VDD1

–

Reference frequency and comparator frequency prescaler and counter 1 V supply

2

FIN

I

Operating frequency divider input pin.

Feedback resistor built-in for AC-coupled inputs.

3

VSS1

–

Ground pin

4RO

O

Test output.

LOW-level output for (1, 0) test bit patter. Leave open for normal operation.

5

TEST

I

Test pin.

Pull-down resistor built-in. Leave open or connect to ground for normal operation.

6DO

O

Phase detector output pin.

Built-in charge pump and tristate output means that this output can be connected to a low-pass filter.

The output polarity is preset for connection to a passive filter.

7

DB

O

Booster signal output for faster locking

8

NC

–

No connection

9

VDD3

–

Phase comparator, charge pump and booster signal 3 V supply

10

VDD2

–

Shift register and latch 1 V supply.

Should be kept at the same potential as VDD1.

11

OPR

I

Power-save control pin.

Operation when HIGH, standby mode when LOW.

12

DATA

I

Control data input pin

13

CLK

I

Control data clock input pin

14

LE

I

Control data latch enable signal input pin

15

XOUT

O

Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can

be connected to XIN. The clock is also output on XOUT.

Feedback resistor built-in for AC-coupled inputs.

16

XIN

I

11 BIT

R COUNTER

PHASE

DETECTOR

CHARGE

PUMP

18 BIT

N COUNTER

VDD1

DATA

RO

VSS

XOUT

LE

CLK

TEST

DB

DO

18 BIT LATCH

11 BIT LATCH

22 BIT

SHIFT REGISTER

XIN

1/8

PRESCALER

VDD2

AREA

VDD2

AREA

VDD1

AREA

BOOSTER

S. G.

LATCH

SELECTER

FIN

WINDOW

GENERATOR

OPR

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

∗

VDD1

AREA

VDD2

AREA

VDD3

AREA

VDD2

VDD3