SM5165AV

NIPPON PRECISION CIRCUITS—7

Reference counter frequency divider setting

Bits 1 to 7 and bits 21 and 22 have no meaning. These bits should be set to 0.

Bits 8 and 9 are used for testing at the manufacturers and should be set to 1 and 0, respectively, for normal

operation.

Input data example

Boost-up Signal

No

meaning

12

345

678

9

10

11

12

13

14

15

16

17

MSB

DATA

18

19

20

21

22

23

LSB

222

222

22

222

10

98

765

43

210

Reference counter

(11-bit : 5 to 8191)

Latch select bit. Set "0"

Test bits

No meaning

NR

Xtal

f

CH

-----------

Xtal

f

R

3

×

---------------

12.8

0.025 3

⁄

--------------------

1536

8

192

×

==

=

=

=

12

345

678

9

10

11

12

13

14

15

16

17

MSB

18

19

20

21

22

23

LSB

222

222

22

222

10

98

765

43

210

00

000

001

00

001

100

0

00

000

0

Input

Data

No

meaning

Reference counter

(11-bit : 5 to 8191)

Latch select bit. Set "0"

Test bits

No meaning

When the PLL starts up with some phase tolerance, a

level signal is output on pin DB. When the PLL

phase error comes within the tolerance before in

lock, output DB goes high impedance.

When the PLL starts up, the signal on DB charges

the low-pass filter capacitor in anticipation of high-

speed locking. After the boost-up signal is output and

the PLL phase error comes within tolerance, the

boost-up circuit stops and operation continues when

goes HIGH once only. After the boost-up circuit

stops, new data is written and the boost-up signal is

not output even if the VCO is not in lock.

FR

FV

Phase detector

error correction signal

WINDOWN

DB

∗∗

∗

∗

(High impedance)

(High impedance)

(HIGH level output)

∗

()