M37270 datasheet(39/94 Pages) MITSUBISHI

39 / 94 page

MITSUBISHI MICROCOMPUTERS

M37270MF-XXXSP

M37270EF-XXXSP, M37270EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Fig. 40. Structure of I2C control register

BSEL1 BSEL0 10 BIT

SAD

ALS

ES0 BC2 BC1 BC0

Connection control bits

between I2C-BUS

interface and ports

b6 Connection port

None

SCL1, SDA1

SCL2, SDA2

SCL1, SDA1,

SCL2, SDA2

I2C control register

(S1D : address 00F916)

Bit counter (Number of

transmit/receive bits)

b2 b1 b0

0 : 8

1 : 7

0 : 6

1 : 5

0 : 4

1 : 3

0 : 2

1 : 1

I2C-BUS interface use

enable bit

0 : Disabled

1 : Enabled

Data format selection bit

0 : Addressing format

1 : Free data format

Addressing format

selection bit

0 : 7-bit addressing

format

1 : 10-bit addressing

format

(5) I2C Status Register

The I2C status register (address 00F816) controls the I2C-BUS inter-

face status. The low-order 4 bits are read-only bits and the high-

order 4 bits can be read out and written to.

s Bit 0: Last receive bit (LRB)

This bit stores the last bit value of received data and can also be

used for ACK receive confirmation. If ACK is returned when an ACK

clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit

is set to “1.” Except in the ACK mode, the last bit value of received

data is input. The state of this bit is changed from “1” to “0” by execut-

ing a write instruction to the I2C data shift register (address 00F616).

s Bit 1: General call detecting flag (AD0)

This bit is set to “1” when a general callV whose address data is all “0”

is received in the slave mode. By a general call of the master device,

every slave device receives control data after the general call. The

AD0 bit is set to “0” by detecting the STOP condition or START con-

dition.

VGeneral call: The master transmits the general call address “0016”

to all slaves.

s Bit 2: Slave address comparison flag (AAS)

This flag indicates a comparison result of address data.

In the slave receive mode, when the 7-bit addressing format is

selected, this bit is set to “1” in one of the following conditions.

•The address data immediately after occurrence of a START

condition agrees with the slave address stored in the high-order

7 bits of the I2C address register (address 00F716).

•A general call is received.

In the slave reception mode, when the 10-bit addressing format is

selected, this bit is set to “1” with the following condition.

•When the address data is compared with the I2C address

bytes agree.

The state of this bit is changed from “1” to “0” by executing a write

instruction to the I2C data shift register (address 00F616).

Fig. 39. Connection port control by BSEL0 and BSEL1

“0”

“1” BSEL0

SCL1/P11

SCL2/P12

“0”

“1” BSEL1

“0”

“1” BSEL0

SDA1/P13

SDA2/P14

“0”

“1” BSEL1

Multi-master

I2C-BUS

interface

SCL

SDA

Note: When using multi-master I2C-BUS interface,

set bits 3 and 4 of the serial I/O mode register

(address 021316) to “1.”

1 :

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