ASM705, ASM706, ASM707, ASM708, ASM813L

http://onsemi.com

7

Application Information

output no longer pulls down; it becomes indeterminate. To

avoid the possibility that stray charges build up and force

RESET to the wrong state, a pull−down resistor should be

connected to the RESET pin, thus draining such charges to

ground and holding RESET low. The resistor value is not

critical. A 100 k

W resistor will pull RESET to ground

without loading it.

Bi−directional Reset Pin Interfacing

The ASM705/6/7/8 can interface with

mP/mC

bi−directional reset pins by connecting a 4.7 k

W resistor in

series with the RESET output and the

mP/mC bi−directional

RESET pin.

Figure 5. Bi−directional Reset Pin Interfacing

Monitoring Voltages Other Than VCC

using the Power Fail circuitry. If a resistive divider is

connected from the voltage to be monitored to the Power

Fail input (PFI), the PFO will go LOW if the voltage at PFI

goes below 1.25 V reference. Should hysteresis be desired,

connect a resistor (equal to approximately 10 times the sum

of the two resistors in the divider) between the PFI and PFO

pins. A capacitor between PFI and GND will reduce circuit

sensitivity to input high−frequency noise. If it is desired to

output is to be connected to the MR.

Figure 6. Monitoring +5 V and an

Monitoring a Negative Voltage

The Power−Fail circuitry can also monitor a negative

supply rail. When the negative rail is OK, PFO will be LOW,

and when the negative rail is failing (not negative enough),

PFO goes HIGH (the opposite of when positive voltages are

monitored). To trigger a reset, these outputs need to be

inverted: adding the resistors and transistor as shown

achieves this. The RESET output will then have the same

sense as for positive voltages: good = HIGH, bad = LOW. It

should be noted that this circuit’s accuracy depends on the

Figure 7. Monitoring a Negative Voltage