MT8870 datasheet(2/12 Pages) MITEL

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MT8870D/MT8870D-1 ISO2-CMOS

4-12

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

IN+

Non-Inverting Op-Amp (Input).

IN-

Inverting Op-Amp (Input).

Gain Select. Gives access to output of front end differential amplifier for connection of

feedback resistor.

VRef

Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 6

and Fig. 10).

INH

Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C

and D. This pin input is internally pulled down.

PWDN

Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This

pin input is internally pulled down.

OSC1

Clock (Input).

OSC2

Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2

completes the internal oscillator circuit.

910

VSS

Ground (Input). 0V typical.

TOE

Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is

pulled up internally.

11-

12-

Q1-Q4

Three State Data (Output). When enabled by TOE, provide the code corresponding to the

last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high

impedance.

StD

Delayed Steering (Output).Presents a logic high when a received tone-pair has been

registered and the output latch updated; returns to logic low when the voltage on St/GT falls

below VTSt.

ESt

Early Steering (Output). Presents a logic high once the digital algorithm has detected a

valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to

return to a logic low.

St/GT

Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at

St causes the device to register the detected tone pair and update the output latch. A

voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to

reset the external steering time-constant; its state is a function of ESt and the voltage on St.

VDD

Positive power supply (Input). +5V typical.

No Connection.

IN+

IN-

VRef

INH

PWDN

OSC1

OSC2

VSS

VDD

St/GT

ESt

StD

TOE

18 PIN CERDIP/PLASTIC DIP/SOIC

IN+

IN-

VRef

INH

PWDN

OSC1

OSC2

VSS

20 PIN SSOP/TSSOP

VDD

St/GT

ESt

StD

TOE

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