MT8920BC datasheet(17/24 Pages) MITEL

17 / 24 page

CMOS

MT8920B

3-19

† Timing is over recommended temperature & power supply voltages.

‡ Typical ﬁgures are at 25

°C, V

DD=5V, tCLK=244 ns, tCH=tCL=122 ns and are for design aid only: not guaranteed and not subject to production

testing.

††The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.

(1) tcwm is equal to tCH or tCL whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having tCHmin=70ns

or tCLmin=70ns.

(2) Worst case access when memory contention occurs.

Figure 14 - Mode 1 Parallel Bus Timing

† During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.

AC Electrical Characteristics†- Mode 1 Parallel Bus Timing (see Fig. 14)

(VCC=5.0V ±5%,TA=-40 to 85°C)

Characteristics

Sym

Min

Typ‡

Max

Units

Test Conditions

Address to DS (CS) Low††

tARDS

0ns

2R/W to DS (CS) Low††

tRWDS

DS (CS) Low to DTACK Low††

tRDS

1,2

tcwm

tCLK

2*tCLK

Load C

Valid Data to DTACK Low (Read)

tRD

tcwm

-30

Load A, CL=130pF, RL=740Ω

DS High to DTACK High

tDAR

Load C, CL=50pF

DS High to Data High Imped.(Read)

tDHZ

045

Load A, CL=130pF, RL=740Ω

DS High to CS High

tCSH

0ns

Data Hold Time (Write)

tDHT

0ns

Input Data Valid after DS

tDST

tcwm

-30

Address Hold Time††

tADHT

A0 - A5

CS (IACK†)

R/W

DTACK

D0 - D7

tADHT

tARDS

tRWDS

tRDS

tRD

tDST

tDHT

DATA IN

DATA OUT

tDHZ

tDAR

tCSH

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