3-4

Figure 2 - Pin Connections

Pin Description

Pin #

Name

1

C4i

4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial

bus.

2

F0i

Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS

stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of

a frame.

3

IACK

Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is

an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will

MS1

Mode Select 1 (Mode 2,3). This input is used to select the device operating modes. A low

applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)

4

STi0

ST-BUS Input 0. This is the input for the 2048 kbit/s ST-BUS serial data stream.

5

CS

Chip Select. This active low input is used to select the STPA for a parallel access .

6

DS

Data Strobe (Mode 1). This active low input indicates to the STPA that valid data is on the data

bus during a write operation or that the STPA must output valid data on the data bus during a

read operation.

OE

Output Enable (Mode 2). This active low input enables the data bus driver outputs.

OE

Output Enable (Mode 3). This active low output indicates that the selected device is to be

read and that the data bus is available for data transfer.

7R/W

Read/Write (Mode 1,2). This input defines the data bus transfer as a read (R/W = 1) or a write

(R/W= 0) cycle.

WE

Write Enable (Mode 3). This active low output indicates the data on the data bus is to be

written into the selected location of an external device.

8-12

A0-A4 Address Bus (Mode 1,2). These inputs are used to select the internal registers and two-port

memories of the STPA.

A0-A4 Address Bus (Mode 3). These address outputs are generated by the STPA and reflect the

position in internal RAM where the information will be fetched from or stored in. Addresses

generated in this mode are used to access external devices for direct memory transfer.

28 PIN J-LEAD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

28

27

26

25

24

23

22

21

C4i

F0i

IACK, MS1

STi0

CS

DS, OE

R/W, WE

A0

A1

A2

A3

A4

A5, STCH

VSS

VDD

MMS

DTACK, BUSY, DCS

IRQ, 24/32

STo1

STo0

D7

D6

D5

D4

D3

D2

D1

D0

28 PIN PDIP/CERDIP/SOIC

5

6

7

8

9

10

11

25

24

23

22

21

20

19

•

IRQ, 24/32

STo1

STo0

D7

D6

D5

D4

CS

DS, OE

R/W, WE

A0

A1

A2

A3