MT8960/61/62/63/64/65/66/67

6-31

(See Figures 9a, 9b, 9c)

Note 3:

The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to

C2i. The A/D and D/A functions are unaffected by changes in clock frequency.

Note 4:

This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i will give an

undetermined state to to the internally synchronized enable signal.

* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics (cont’d)

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

17

D

I

G

I

T

A

L

Propagation Delay

SD

Clock to SD Output

400

ns

18

SD Output Fall Time

SD

200

ns

19

SD Output Rise Time

SD

400

ns

20

Digital Loopback

Time DSTi to DSTo

122

ns

Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

1

A

N

A

L

O

G

the overload decision level at

the codec

4.829

5.000

Level at codec:

µ-Law: 3.17 dBm0

A-Law: 3.14 dBm0

See Note 6

2

Absolute Gain (0dB setting)

-0.25

+0.25

dB

0 dBm0 @ 1004 Hz

3

Absolute Gain (+1dB to +7dB

settings)

-0.35

+0.35

dB

from nominal,

@ 1004 Hz

4

Gain Variation

With Temp

0.01

dB

With Supplies

0.04

dB/V

5

Gain Tracking

(See Figure 12)

CCITT G712

(Method 1)

-0.25

-0.25

-0.50

+0.25

+0.25

+0.50

dB

dB

dB

Sinusoidal Level:

+3 to -20 dBm0

Noise Signal Level:

-10 to -55 dBm0

-55 to -60 dBm0

CCITT G712

(Method 2)

AT&T

-0.25

-0.50

-1.50

+0.25

+0.50

+1.50

dB

dB

dB

Sinusoidal Level:

+3 to -40 dBm0

-40 to -50 dBm0

-50 to -55 dBm0

6

Quantization

Distortion

(See Figure 13)

CCITT G712

(Method 1)

28.00

35.60

33.90

29.30

14.20

dB

dB

dB

dB

dB

Noise Signal Level:

-3 dBm0

-6 to -27 dBm0

-34 dBm0

-40 dBm0

-55 dBm0