MT8977AP datasheet(17/26 Pages) MITEL

17 / 26 page

Preliminary Information

ISO-CMOS

MT8977

4-115

shows the MT8977 interfaced to a parallel bus

structure using two STPA‘s operating in modes 1 and

The first STPA operating in mode 2 (MMS=0,

MS1=1, 24/32=0),

routes

data

and/or

voice

information between the parallel telecom bus and the

T1 or CEPT link via DSTi and DSTo.

The second

STPA, operating in mode 1 (MMS = 1 ) provides

access from the signalling and link control bus to the

MT8977 status and control channels. All signalling

and link functions may be controlled easily through

the STPA transmit RAM’s Tx0, Tx1,

while status

information is read at receive RAM Rx0. In addition,

interrupts can be set up to notify the system in case

of slips, loss of sync, alarms, violations, etc.

Note: the configurations shown in Figures 11 and 12

using the MT8940/41 may not meet specific jitter

performance requirements.

A more sophisticated

PLL

line

interface

unit

with

transmit

jitter

attenuator may be required for applications designed

to meet specific standards.

Figure 11 - Typical ESF Configuration

•

MT8980

MT8977

MT8940/41

MH89761

MT8952

Micro

Processor

STi3

STo3

STo0

STi0

STi1

STo2

C4i

F0i

CDSTi

CKi

Clock

Extractor

DSTi

DSTo

CSTi0

CSTi1

F0i

C2i

C1.5i

TxFDL

TxFDLClk

RxFDL

RxFDLClk

E1.5i

TxA

TxB

RxA

RxB

RxD

TxSF

RxSF

E8Ko

Line

Receiver

1.544

MHz

CVb

F0i

C2o

F0b

C4b

C8Kb

12.355/12.352

MHz Osc.

16.388/16.384

MHz Osc.

MT8940/41

STo1

CSTo

Line

Driver

Equa-

lizer

CDSTo

TxCEN

RxCEN

MT8977AP Datasheet(PDF) 17 Page - Mitel Networks Corporation

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