MT90500AL datasheet(22/159 Pages) MITEL

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MT90500

Table 5 - Master Clock, Test, and Power Pins

Pin #

Pin Name

I/O

Type

Description

MCLK

TTL PU

Master Clock. This signal drives the internal logic (including the RX_SAR and

the TX_SAR) and the external memory (through MEMCLK). 60 MHz for most

applications. MCLK should be more than 5 times CLKx1, and should be more

than 3 times FNXI.

RESET

5V TTL

Schmitt PU

Chip reset signal (active LOW). Note that the MT90500 is synchronously reset,

and that MCLK should be applied during reset. To asynchronously tristate

outputs, assert the TRISTATE pin. The TRST pin (JTAG reset) should also be

asserted LOW during chip reset. Reset should last at least 2

µs when MCLK is

60 MHz. Also see SRES bit in register 0000h.

TMS

3.3V CMOS

JTAG Test Mode Select signal.

TCK

3.3V CMOS

JTAG Test Clock.

TDI

3.3V CMOS

JTAG Test Data In.

TDO

3.3V, 4mA

JTAG Test Data Out.

Note: TDO is tristated by TRISTATE pin.

TRST

3.3V CMOS

JTAG Test Reset input (active LOW). Should be asserted LOW on power-up

and during reset. Must be HIGH for JTAG boundary-scan operation. Note:

This pin has an internal pull-down.

1, 7, 16, 29, 43,

61, 86, 91, 110,

119, 129, 139,

151, 163, 172,

182, 197, 213,

229

IO_VSS

GND

Ground for I/O logic.

100, 141, 161

CORE_VSS

GND

Ground for core logic.

20, 40, 80, 201,

221

RING_VSS

GND

Ground for core logic.

92, 111, 120,

132, 145, 157,

169, 181

IO_VDD_3V

PWR

Power for I/O logic (3.3 V).

2, 13, 24, 42,

60, 88, 183,

207, 225, 240

IO_VDD_5V

PWR

Power for I/O logic (5 V).

101, 140, 160

CORE_VDD_3V

PWR

Power for core logic (3.3 V).

21, 41, 81, 200,

220

RING_VDD_3V

PWR

Power for core logic (3.3 V).

IC TEST, must be grounded.

TRISTATE

3.3V CMOS

3.3V ONLY

Output Tristate Control. Asynchronously tristates all output pins when LOW.

Can be asserted LOW on power-up and during reset. Pull up to 3.3V for

normal operation. NOT 5V TOLERANT.

MT90500AL Datasheet(PDF) 22 Page - Mitel Networks Corporation

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