Preliminary Information

MT9125

8-29

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Data Clock High

160

ns

2

Data Clock Low

160

ns

3

BCLK Period

400

7900

ns

4

Data Output Delay (excluding

first bit)

60

ns

5

Output Active to High Z

60

ns

6

Strobe Signal Setup

80

80

ns

7

Strobe Signal Hold

80

80

ns

8

Strobe period relative to MCLK

(ENB1, ENB2, ENA)

50

ns

9

Data Input Setup

50

ns

10

Data Input Hold

50

ns

11

Strobe to Data Delay (first bit)

60

ns

12

F0i Setup

50

122

150

ns

13

F0i Hold

50

122

150

ns

14

MCLK (C4i) duty cycle

x100

40

50

60

%

15

MCLK (C4i) period

190

244.2

ns

16

Data Output delay

125

ns

17

Data in Hold time

50

ns

18

Data in Setup time

50

ns